Area Array Interconnection Handbook
☆☆☆☆☆
(0 opinii)
Najniższa cena (z dostawą)
7 174,00 JPY
Typowa cena362,20 PLN
Najniższa (90 dni)49,99 PLN
Liczba ofert2
Ostatnia aktualizacja4 godziny temu
| Sprzedawca | Cena produktu | Dostawa | Razem | Dostępność | Aktualizacja | |
|---|---|---|---|---|---|---|
| SP Springer Nature Author | 7 149,00 JPY | 25,00 JPY | 7 174,00 JPY | Dostępny | 4 godziny temu | Zobacz ofertę |
| SP SpringerNatureLink Shop INT | 59,00 EUR | 15,00 EUR | 74,00 EUR | Dostępny | 16 godzin temu | Zobacz ofertę |
Ceny i dostępność mogą ulec zmianie. Ostatnia aktualizacja: 08.08.2026 23:12.
0,0
☆☆☆☆☆
0 opinii
5★
0%
4★
0%
3★
0%
2★
0%
1★
0%
Opinie o produkcie
Brak opinii — bądź pierwszy!
Microelectronic packaging has been recognized as an important "enabler" for the solid state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.