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Energy Efficient High Performance Processors

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Energy Efficient High Performance Processors
Lowest price (incl. delivery)
17 188,00 JPY
Typical price1 107,15 PLN
Lowest (90 days)87,50 PLN
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Last updated1 settimana fa
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2026-08-08 2026-08-15
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2026-08-0887,50
2026-08-1587,50
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SP SpringerNatureLink Shop INT 17 159,00 JPY 29,00 JPY 17 188,00 JPY Disponibile 1 settimana fa View offer
SP Springer Nature Author 17 159,00 JPY free 17 159,00 JPY Disponibile 1 settimana fa View offer
SP SpringerNatureLink Shop INT 119,99 USD 19,00 USD 138,99 USD Disponibile 1 settimana fa View offer
SP SpringerNatureLink Shop INT 129,99 USD 19,00 USD 148,99 USD Disponibile 1 settimana fa View offer
SP SpringerNatureLink Shop INT 129,99 USD 15,00 USD 144,99 USD Disponibile 1 settimana fa View offer
SP SpringerNatureLink Shop INT 142,00 EUR 25,00 EUR 167,00 EUR Disponibile 1 settimana fa View offer

I prezzi e la disponibilità possono variare. Ultimo aggiornamento: 08.08.2026 22:18.

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This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

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